{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 02 19:54:18 2007 " "Info: Processing started: Sun Dec 02 19:54:18 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off single_cycle_datapath -c single_cycle_datapath " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off single_cycle_datapath -c single_cycle_datapath" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "single_cycle_datapath EP2C20F484C7 " "Info: Selected device EP2C20F484C7 for design \"single_cycle_datapath\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "2976 Top " "Info: Previous placement does not exist for 2976 of 2976 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "FPGA_Clock (placed in PIN A12 (CLK9, LVDSCLK4p, Input)) " "Info: Automatically promoted node FPGA_Clock (placed in PIN A12 (CLK9, LVDSCLK4p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G10 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G10" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { FPGA_Clock } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FPGA_Clock" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 720 232 248 888 "FPGA_Clock" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FPGA_Clock } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FPGA_Clock } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.378 ns register register " "Info: Estimated most critical path is register to register delay of 4.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Data_Memory:inst26\|sram_not_oe 1 REG LAB_X27_Y12 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X27_Y12; Fanout = 3; REG Node = 'Data_Memory:inst26\|sram_not_oe'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Data_Memory:inst26|sram_not_oe } "NODE_NAME" } } { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.628 ns) + CELL(0.544 ns) 2.172 ns Data_Memory:inst26\|Selector18~232 2 COMB LAB_X36_Y13 1 " "Info: 2: + IC(1.628 ns) + CELL(0.544 ns) = 2.172 ns; Loc. = LAB_X36_Y13; Fanout = 1; COMB Node = 'Data_Memory:inst26\|Selector18~232'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.172 ns" { Data_Memory:inst26|sram_not_oe Data_Memory:inst26|Selector18~232 } "NODE_NAME" } } { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.589 ns) + CELL(0.521 ns) 4.282 ns Data_Memory:inst26\|Selector18~233 3 COMB LAB_X27_Y12 1 " "Info: 3: + IC(1.589 ns) + CELL(0.521 ns) = 4.282 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'Data_Memory:inst26\|Selector18~233'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.110 ns" { Data_Memory:inst26|Selector18~232 Data_Memory:inst26|Selector18~233 } "NODE_NAME" } } { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 4.378 ns Data_Memory:inst26\|sram_not_oe 4 REG LAB_X27_Y12 3 " "Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 4.378 ns; Loc. = LAB_X27_Y12; Fanout = 3; REG Node = 'Data_Memory:inst26\|sram_not_oe'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Data_Memory:inst26|Selector18~233 Data_Memory:inst26|sram_not_oe } "NODE_NAME" } } { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.161 ns ( 26.52 % ) " "Info: Total cell delay = 1.161 ns ( 26.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.217 ns ( 73.48 % ) " "Info: Total interconnect delay = 3.217 ns ( 73.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.378 ns" { Data_Memory:inst26|sram_not_oe Data_Memory:inst26|Selector18~232 Data_Memory:inst26|Selector18~233 Data_Memory:inst26|sram_not_oe } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "6 " "Info: Average interconnect usage is 6% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "23 X25_Y0 X37_Y13 " "Info: Peak interconnect usage is 23% of the available device resources in the region that extends from location X25_Y0 to location X37_Y13" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Info: Fitter routing operations ending: elapsed time is 00:00:05" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "4 " "Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_CE_N GND " "Info: Pin SRAM_CE_N has GND driving its datain port" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_CE_N } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 680 672 848 696 "SRAM_CE_N" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_CE_N } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_CE_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_UB_N GND " "Info: Pin SRAM_UB_N has GND driving its datain port" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_UB_N } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 728 672 848 744 "SRAM_UB_N" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_UB_N } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_UB_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_LB_N GND " "Info: Pin SRAM_LB_N has GND driving its datain port" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_LB_N } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 744 672 848 760 "SRAM_LB_N" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_LB_N } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_LB_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_Addr\[17\] GND " "Info: Pin SRAM_Addr\[17\] has GND driving its datain port" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Addr[17] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Addr\[17\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 664 672 857 680 "SRAM_Addr\[17..0\]" "" } { 656 560 672 672 "SRAM_Addr\[17..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Addr[17] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Addr[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "Data_Memory:inst26\|sram_not_we (inverted) " "Info: Following pins have the same output enable: Data_Memory:inst26\|sram_not_we (inverted)" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[15\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[15\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[15] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[15\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[15] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[15] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[13\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[13\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[13] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[13\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[13] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[13] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[11\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[11\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[11] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[11\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[11] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[9\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[9\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[9] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[9\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[9] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[9] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[7] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[7\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[5] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[5\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[3] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[3\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[1] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[1\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[14\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[14\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[14] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[14\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[14] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[14] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[12\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[12\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[12] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[12\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[12] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[12] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[10\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[10\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[10] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[10\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[10] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[10] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[8\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[8\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[8] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[8\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[8] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[6] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[6\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[4] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[4\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[2] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[2\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_Data\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin SRAM_Data\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { SRAM_Data[0] } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_Data\[0\]" } } } } { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 648 672 853 664 "SRAM_Data\[7..0\]" "" } { 632 672 859 648 "SRAM_Data\[15..8\]" "" } { 624 560 672 640 "SRAM_Data\[15..8\]" "" } { 640 560 672 656 "SRAM_Data\[7..0\]" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAM_Data[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.fit.smsg " "Info: Generated suppressed messages file F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "214 " "Info: Allocated 214 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 02 19:54:43 2007 " "Info: Processing ended: Sun Dec 02 19:54:43 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Info: Elapsed time: 00:00:25" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
