{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 02 19:53:45 2007 " "Info: Processing started: Sun Dec 02 19:53:45 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off single_cycle_datapath -c single_cycle_datapath " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off single_cycle_datapath -c single_cycle_datapath" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hex2sevenseg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file hex2sevenseg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex2sevenseg " "Info: Found entity 1: hex2sevenseg" {  } { { "hex2sevenseg.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/hex2sevenseg.v" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "single_cycle_datapath.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file single_cycle_datapath.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 single_cycle_datapath " "Info: Found entity 1: single_cycle_datapath" {  } { { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PC_Register.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file PC_Register.v" { { "Info" "ISGN_ENTITY_NAME" "1 PC_Register " "Info: Found entity 1: PC_Register" {  } { { "PC_Register.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/PC_Register.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "instruction_memory.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file instruction_memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 Instruction_Memory " "Info: Found entity 1: Instruction_Memory" {  } { { "instruction_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/instruction_memory.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Register_File.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Register_File.v" { { "Info" "ISGN_ENTITY_NAME" "1 Register_File " "Info: Found entity 1: Register_File" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 12 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ALU.v" { { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Info: Found entity 1: ALU" {  } { { "ALU.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/ALU.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "r_format control_unit.v(45) " "Warning (10236): Verilog HDL Implicit Net warning at control_unit.v(45): created implicit net for \"r_format\"" {  } { { "control_unit.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/control_unit.v" 45 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "i_format control_unit.v(46) " "Warning (10236): Verilog HDL Implicit Net warning at control_unit.v(46): created implicit net for \"i_format\"" {  } { { "control_unit.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/control_unit.v" 46 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control_unit.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file control_unit.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_unit " "Info: Found entity 1: control_unit" {  } { { "control_unit.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/control_unit.v" 14 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "data_memory.v(65) " "Warning (10273): Verilog HDL warning at data_memory.v(65): extended using \"x\" or \"z\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 65 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "data_memory.v(76) " "Warning (10268): Verilog HDL information at data_memory.v(76): Always Construct contains both blocking and non-blocking assignments" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 76 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_memory.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 Data_Memory " "Info: Found entity 1: Data_Memory" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file add4.v" { { "Info" "ISGN_ENTITY_NAME" "1 add4 " "Info: Found entity 1: add4" {  } { { "add4.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/add4.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Info: Found entity 1: alu_control" {  } { { "alu_control.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/alu_control.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "calc_bta.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file calc_bta.v" { { "Info" "ISGN_ENTITY_NAME" "1 calc_BranchTargetAddress " "Info: Found entity 1: calc_BranchTargetAddress" {  } { { "calc_bta.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/calc_bta.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "calc_jump_address.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file calc_jump_address.v" { { "Info" "ISGN_ENTITY_NAME" "1 calc_JumpAddress " "Info: Found entity 1: calc_JumpAddress" {  } { { "calc_jump_address.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/calc_jump_address.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sign_extend_1632.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sign_extend_1632.v" { { "Info" "ISGN_ENTITY_NAME" "1 sign_extend_1632 " "Info: Found entity 1: sign_extend_1632" {  } { { "sign_extend_1632.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/sign_extend_1632.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "two_by_5_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file two_by_5_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 Two_by_5_mux " "Info: Found entity 1: Two_by_5_mux" {  } { { "two_by_5_mux.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/two_by_5_mux.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "two_by_16_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file two_by_16_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 Two_by_16_mux " "Info: Found entity 1: Two_by_16_mux" {  } { { "two_by_16_mux.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/two_by_16_mux.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "two_by_32_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file two_by_32_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 Two_by_32_mux " "Info: Found entity 1: Two_by_32_mux" {  } { { "two_by_32_mux.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/two_by_32_mux.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "eight_by_16_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file eight_by_16_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 Eight_by_16_mux " "Info: Found entity 1: Eight_by_16_mux" {  } { { "eight_by_16_mux.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/eight_by_16_mux.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pc_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pc_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 pc_mux " "Info: Found entity 1: pc_mux" {  } { { "pc_mux.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/pc_mux.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ledg_buffers.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ledg_buffers.v" { { "Info" "ISGN_ENTITY_NAME" "1 ledg_buffers " "Info: Found entity 1: ledg_buffers" {  } { { "ledg_buffers.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/ledg_buffers.v" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ledr_buffers.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ledr_buffers.v" { { "Info" "ISGN_ENTITY_NAME" "1 ledr_buffers " "Info: Found entity 1: ledr_buffers" {  } { { "ledr_buffers.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/ledr_buffers.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "single_cycle_datapath " "Info: Elaborating entity \"single_cycle_datapath\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "single_cycle_datapath " "Warning: Processing legacy GDF or BDF entity \"single_cycle_datapath\" with Max+Plus II bus and instance naming rules" {  } { { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex2sevenseg hex2sevenseg:Hex3 " "Info: Elaborating entity \"hex2sevenseg\" for hierarchy \"hex2sevenseg:Hex3\"" {  } { { "single_cycle_datapath.bdf" "Hex3" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { -448 -64 32 -288 "Hex3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Two_by_16_mux Two_by_16_mux:inst23 " "Info: Elaborating entity \"Two_by_16_mux\" for hierarchy \"Two_by_16_mux:inst23\"" {  } { { "single_cycle_datapath.bdf" "inst23" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { -592 -224 -72 -496 "inst23" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Eight_by_16_mux Eight_by_16_mux:inst " "Info: Elaborating entity \"Eight_by_16_mux\" for hierarchy \"Eight_by_16_mux:inst\"" {  } { { "single_cycle_datapath.bdf" "inst" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { -592 -448 -272 -400 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PC_Register PC_Register:inst2 " "Info: Elaborating entity \"PC_Register\" for hierarchy \"PC_Register:inst2\"" {  } { { "single_cycle_datapath.bdf" "inst2" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 464 -1264 -1080 560 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pc_mux pc_mux:inst44 " "Info: Elaborating entity \"pc_mux\" for hierarchy \"pc_mux:inst44\"" {  } { { "single_cycle_datapath.bdf" "inst44" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 464 -1504 -1296 592 "inst44" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_unit control_unit:inst34 " "Info: Elaborating entity \"control_unit\" for hierarchy \"control_unit:inst34\"" {  } { { "single_cycle_datapath.bdf" "inst34" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 352 -568 -384 544 "inst34" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Instruction_Memory Instruction_Memory:inst4 " "Info: Elaborating entity \"Instruction_Memory\" for hierarchy \"Instruction_Memory:inst4\"" {  } { { "single_cycle_datapath.bdf" "inst4" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 464 -968 -768 560 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALU ALU:inst31 " "Info: Elaborating entity \"ALU\" for hierarchy \"ALU:inst31\"" {  } { { "single_cycle_datapath.bdf" "inst31" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 592 0 168 688 "inst31" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Register_File Register_File:inst29 " "Info: Elaborating entity \"Register_File\" for hierarchy \"Register_File:inst29\"" {  } { { "single_cycle_datapath.bdf" "inst29" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 672 -320 -96 832 "inst29" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Two_by_32_mux Two_by_32_mux:inst7 " "Info: Elaborating entity \"Two_by_32_mux\" for hierarchy \"Two_by_32_mux:inst7\"" {  } { { "single_cycle_datapath.bdf" "inst7" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 848 -296 -144 944 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Data_Memory Data_Memory:inst26 " "Info: Elaborating entity \"Data_Memory\" for hierarchy \"Data_Memory:inst26\"" {  } { { "single_cycle_datapath.bdf" "inst26" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 592 280 560 784 "inst26" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Two_by_5_mux Two_by_5_mux:inst22 " "Info: Elaborating entity \"Two_by_5_mux\" for hierarchy \"Two_by_5_mux:inst22\"" {  } { { "single_cycle_datapath.bdf" "inst22" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 736 -544 -400 832 "inst22" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sign_extend_1632 sign_extend_1632:inst21 " "Info: Elaborating entity \"sign_extend_1632\" for hierarchy \"sign_extend_1632:inst21\"" {  } { { "single_cycle_datapath.bdf" "inst21" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 848 -544 -400 944 "inst21" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu_control alu_control:inst33 " "Info: Elaborating entity \"alu_control\" for hierarchy \"alu_control:inst33\"" {  } { { "single_cycle_datapath.bdf" "inst33" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 592 -568 -368 688 "inst33" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "calc_BranchTargetAddress calc_BranchTargetAddress:inst32 " "Info: Elaborating entity \"calc_BranchTargetAddress\" for hierarchy \"calc_BranchTargetAddress:inst32\"" {  } { { "single_cycle_datapath.bdf" "inst32" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 184 -1248 -1072 280 "inst32" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add4 add4:inst17 " "Info: Elaborating entity \"add4\" for hierarchy \"add4:inst17\"" {  } { { "single_cycle_datapath.bdf" "inst17" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 328 -1296 -1104 424 "inst17" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "calc_JumpAddress calc_JumpAddress:inst40 " "Info: Elaborating entity \"calc_JumpAddress\" for hierarchy \"calc_JumpAddress:inst40\"" {  } { { "single_cycle_datapath.bdf" "inst40" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 56 -1248 -1008 152 "inst40" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ledg_buffers ledg_buffers:inst1 " "Info: Elaborating entity \"ledg_buffers\" for hierarchy \"ledg_buffers:inst1\"" {  } { { "single_cycle_datapath.bdf" "inst1" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { -200 -1312 -1176 -8 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ledr_buffers ledr_buffers:inst3 " "Info: Elaborating entity \"ledr_buffers\" for hierarchy \"ledr_buffers:inst3\"" {  } { { "single_cycle_datapath.bdf" "inst3" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { -88 -544 -384 8 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PC_Register:inst2\|PC_out\[0\] data_in GND " "Warning (14130): Reduced register \"PC_Register:inst2\|PC_out\[0\]\" with stuck data_in port to stuck value GND" {  } { { "PC_Register.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/PC_Register.v" 18 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PC_Register:inst2\|PC_out\[1\] data_in GND " "Warning (14130): Reduced register \"PC_Register:inst2\|PC_out\[1\]\" with stuck data_in port to stuck value GND" {  } { { "PC_Register.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/PC_Register.v" 18 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_UNINFERRED_RAM_SUMMARY" "2 " "Info: Found 2 instances of uninferred RAM logic" { { "Info" "IOPT_READ_LOGIC_IS_ASYNCHRONOUS" "Register_File:inst29\|registers__dual " "Info: RAM logic \"Register_File:inst29\|registers__dual\" uninferred due to asynchronous read logic" {  } { { "Register_File.v" "registers__dual" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "RAM logic \"%1!s!\" uninferred due to asynchronous read logic" 0 0 "" 0} { "Info" "IOPT_READ_LOGIC_IS_ASYNCHRONOUS" "Register_File:inst29\|registers " "Info: RAM logic \"Register_File:inst29\|registers\" uninferred due to asynchronous read logic" {  } { { "Register_File.v" "registers" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "RAM logic \"%1!s!\" uninferred due to asynchronous read logic" 0 0 "" 0}  } {  } 0 0 "Found %1!d! instances of uninferred RAM logic" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Data_Memory:inst26\|sram_address\[17\] data_in GND " "Warning (14130): Reduced register \"Data_Memory:inst26\|sram_address\[17\]\" with stuck data_in port to stuck value GND" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 76 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|single_cycle_datapath\|Data_Memory:inst26\|curr_state 6 " "Info: State machine \"\|single_cycle_datapath\|Data_Memory:inst26\|curr_state\" contains 6 states" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|single_cycle_datapath\|Data_Memory:inst26\|curr_state " "Info: Selected Auto state machine encoding method for state machine \"\|single_cycle_datapath\|Data_Memory:inst26\|curr_state\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|single_cycle_datapath\|Data_Memory:inst26\|curr_state " "Info: Encoding result for state machine \"\|single_cycle_datapath\|Data_Memory:inst26\|curr_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Data_Memory:inst26\|curr_state.s_wait_cpu " "Info: Encoded state bit \"Data_Memory:inst26\|curr_state.s_wait_cpu\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Data_Memory:inst26\|curr_state.s_write_upper " "Info: Encoded state bit \"Data_Memory:inst26\|curr_state.s_write_upper\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Data_Memory:inst26\|curr_state.s_write_lower " "Info: Encoded state bit \"Data_Memory:inst26\|curr_state.s_write_lower\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Data_Memory:inst26\|curr_state.s_read_upper " "Info: Encoded state bit \"Data_Memory:inst26\|curr_state.s_read_upper\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Data_Memory:inst26\|curr_state.s_read_lower " "Info: Encoded state bit \"Data_Memory:inst26\|curr_state.s_read_lower\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Data_Memory:inst26\|curr_state.s_idle " "Info: Encoded state bit \"Data_Memory:inst26\|curr_state.s_idle\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_idle 000000 " "Info: State \"\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_idle\" uses code string \"000000\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_read_lower 000011 " "Info: State \"\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_read_lower\" uses code string \"000011\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_read_upper 000101 " "Info: State \"\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_read_upper\" uses code string \"000101\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_write_lower 001001 " "Info: State \"\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_write_lower\" uses code string \"001001\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_write_upper 010001 " "Info: State \"\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_write_upper\" uses code string \"010001\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_wait_cpu 100001 " "Info: State \"\|single_cycle_datapath\|Data_Memory:inst26\|curr_state.s_wait_cpu\" uses code string \"100001\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 57 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~216 Register_File:inst29\|registers~216 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~216\" merged to single register \"Register_File:inst29\|registers~216\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~280 Register_File:inst29\|registers~280 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~280\" merged to single register \"Register_File:inst29\|registers~280\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~344 Register_File:inst29\|registers~344 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~344\" merged to single register \"Register_File:inst29\|registers~344\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1112 Register_File:inst29\|registers~1112 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1112\" merged to single register \"Register_File:inst29\|registers~1112\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1176 Register_File:inst29\|registers~1176 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1176\" merged to single register \"Register_File:inst29\|registers~1176\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1240 Register_File:inst29\|registers~1240 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1240\" merged to single register \"Register_File:inst29\|registers~1240\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1304 Register_File:inst29\|registers~1304 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1304\" merged to single register \"Register_File:inst29\|registers~1304\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1368 Register_File:inst29\|registers~1368 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1368\" merged to single register \"Register_File:inst29\|registers~1368\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1432 Register_File:inst29\|registers~1432 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1432\" merged to single register \"Register_File:inst29\|registers~1432\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1496 Register_File:inst29\|registers~1496 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1496\" merged to single register \"Register_File:inst29\|registers~1496\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~120 Register_File:inst29\|registers~120 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~120\" merged to single register \"Register_File:inst29\|registers~120\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1144 Register_File:inst29\|registers~1144 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1144\" merged to single register \"Register_File:inst29\|registers~1144\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~126 Register_File:inst29\|registers~126 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~126\" merged to single register \"Register_File:inst29\|registers~126\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~382 Register_File:inst29\|registers~382 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~382\" merged to single register \"Register_File:inst29\|registers~382\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~510 Register_File:inst29\|registers~510 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~510\" merged to single register \"Register_File:inst29\|registers~510\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1150 Register_File:inst29\|registers~1150 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1150\" merged to single register \"Register_File:inst29\|registers~1150\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1278 Register_File:inst29\|registers~1278 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1278\" merged to single register \"Register_File:inst29\|registers~1278\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1342 Register_File:inst29\|registers~1342 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1342\" merged to single register \"Register_File:inst29\|registers~1342\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1406 Register_File:inst29\|registers~1406 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1406\" merged to single register \"Register_File:inst29\|registers~1406\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1470 Register_File:inst29\|registers~1470 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1470\" merged to single register \"Register_File:inst29\|registers~1470\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1534 Register_File:inst29\|registers~1534 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1534\" merged to single register \"Register_File:inst29\|registers~1534\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1598 Register_File:inst29\|registers~1598 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1598\" merged to single register \"Register_File:inst29\|registers~1598\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~124 Register_File:inst29\|registers~124 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~124\" merged to single register \"Register_File:inst29\|registers~124\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~188 Register_File:inst29\|registers~188 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~188\" merged to single register \"Register_File:inst29\|registers~188\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~252 Register_File:inst29\|registers~252 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~252\" merged to single register \"Register_File:inst29\|registers~252\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~316 Register_File:inst29\|registers~316 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~316\" merged to single register \"Register_File:inst29\|registers~316\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~380 Register_File:inst29\|registers~380 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~380\" merged to single register \"Register_File:inst29\|registers~380\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~444 Register_File:inst29\|registers~444 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~444\" merged to single register \"Register_File:inst29\|registers~444\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~508 Register_File:inst29\|registers~508 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~508\" merged to single register \"Register_File:inst29\|registers~508\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~572 Register_File:inst29\|registers~572 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~572\" merged to single register \"Register_File:inst29\|registers~572\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1276 Register_File:inst29\|registers~1276 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1276\" merged to single register \"Register_File:inst29\|registers~1276\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1404 Register_File:inst29\|registers~1404 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1404\" merged to single register \"Register_File:inst29\|registers~1404\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1532 Register_File:inst29\|registers~1532 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1532\" merged to single register \"Register_File:inst29\|registers~1532\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~122 Register_File:inst29\|registers~122 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~122\" merged to single register \"Register_File:inst29\|registers~122\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~378 Register_File:inst29\|registers~378 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~378\" merged to single register \"Register_File:inst29\|registers~378\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1402 Register_File:inst29\|registers~1402 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1402\" merged to single register \"Register_File:inst29\|registers~1402\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~118 Register_File:inst29\|registers~118 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~118\" merged to single register \"Register_File:inst29\|registers~118\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~374 Register_File:inst29\|registers~374 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~374\" merged to single register \"Register_File:inst29\|registers~374\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1142 Register_File:inst29\|registers~1142 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1142\" merged to single register \"Register_File:inst29\|registers~1142\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1398 Register_File:inst29\|registers~1398 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1398\" merged to single register \"Register_File:inst29\|registers~1398\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~116 Register_File:inst29\|registers~116 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~116\" merged to single register \"Register_File:inst29\|registers~116\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~244 Register_File:inst29\|registers~244 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~244\" merged to single register \"Register_File:inst29\|registers~244\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~372 Register_File:inst29\|registers~372 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~372\" merged to single register \"Register_File:inst29\|registers~372\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~500 Register_File:inst29\|registers~500 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~500\" merged to single register \"Register_File:inst29\|registers~500\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1140 Register_File:inst29\|registers~1140 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1140\" merged to single register \"Register_File:inst29\|registers~1140\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1268 Register_File:inst29\|registers~1268 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1268\" merged to single register \"Register_File:inst29\|registers~1268\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1396 Register_File:inst29\|registers~1396 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1396\" merged to single register \"Register_File:inst29\|registers~1396\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1524 Register_File:inst29\|registers~1524 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1524\" merged to single register \"Register_File:inst29\|registers~1524\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~114 Register_File:inst29\|registers~114 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~114\" merged to single register \"Register_File:inst29\|registers~114\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~178 Register_File:inst29\|registers~178 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~178\" merged to single register \"Register_File:inst29\|registers~178\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~242 Register_File:inst29\|registers~242 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~242\" merged to single register \"Register_File:inst29\|registers~242\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~306 Register_File:inst29\|registers~306 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~306\" merged to single register \"Register_File:inst29\|registers~306\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~370 Register_File:inst29\|registers~370 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~370\" merged to single register \"Register_File:inst29\|registers~370\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~434 Register_File:inst29\|registers~434 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~434\" merged to single register \"Register_File:inst29\|registers~434\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~498 Register_File:inst29\|registers~498 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~498\" merged to single register \"Register_File:inst29\|registers~498\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~562 Register_File:inst29\|registers~562 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~562\" merged to single register \"Register_File:inst29\|registers~562\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1202 Register_File:inst29\|registers~1202 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1202\" merged to single register \"Register_File:inst29\|registers~1202\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1266 Register_File:inst29\|registers~1266 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1266\" merged to single register \"Register_File:inst29\|registers~1266\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1330 Register_File:inst29\|registers~1330 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1330\" merged to single register \"Register_File:inst29\|registers~1330\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1394 Register_File:inst29\|registers~1394 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1394\" merged to single register \"Register_File:inst29\|registers~1394\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1458 Register_File:inst29\|registers~1458 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1458\" merged to single register \"Register_File:inst29\|registers~1458\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1522 Register_File:inst29\|registers~1522 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1522\" merged to single register \"Register_File:inst29\|registers~1522\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1586 Register_File:inst29\|registers~1586 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1586\" merged to single register \"Register_File:inst29\|registers~1586\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~112 Register_File:inst29\|registers~112 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~112\" merged to single register \"Register_File:inst29\|registers~112\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~176 Register_File:inst29\|registers~176 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~176\" merged to single register \"Register_File:inst29\|registers~176\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~240 Register_File:inst29\|registers~240 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~240\" merged to single register \"Register_File:inst29\|registers~240\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~304 Register_File:inst29\|registers~304 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~304\" merged to single register \"Register_File:inst29\|registers~304\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~368 Register_File:inst29\|registers~368 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~368\" merged to single register \"Register_File:inst29\|registers~368\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~432 Register_File:inst29\|registers~432 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~432\" merged to single register \"Register_File:inst29\|registers~432\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~496 Register_File:inst29\|registers~496 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~496\" merged to single register \"Register_File:inst29\|registers~496\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~560 Register_File:inst29\|registers~560 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~560\" merged to single register \"Register_File:inst29\|registers~560\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1136 Register_File:inst29\|registers~1136 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1136\" merged to single register \"Register_File:inst29\|registers~1136\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1200 Register_File:inst29\|registers~1200 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1200\" merged to single register \"Register_File:inst29\|registers~1200\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1264 Register_File:inst29\|registers~1264 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1264\" merged to single register \"Register_File:inst29\|registers~1264\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1328 Register_File:inst29\|registers~1328 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1328\" merged to single register \"Register_File:inst29\|registers~1328\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1392 Register_File:inst29\|registers~1392 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1392\" merged to single register \"Register_File:inst29\|registers~1392\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1456 Register_File:inst29\|registers~1456 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1456\" merged to single register \"Register_File:inst29\|registers~1456\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1520 Register_File:inst29\|registers~1520 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1520\" merged to single register \"Register_File:inst29\|registers~1520\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~110 Register_File:inst29\|registers~110 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~110\" merged to single register \"Register_File:inst29\|registers~110\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~238 Register_File:inst29\|registers~238 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~238\" merged to single register \"Register_File:inst29\|registers~238\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~366 Register_File:inst29\|registers~366 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~366\" merged to single register \"Register_File:inst29\|registers~366\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~494 Register_File:inst29\|registers~494 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~494\" merged to single register \"Register_File:inst29\|registers~494\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1262 Register_File:inst29\|registers~1262 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1262\" merged to single register \"Register_File:inst29\|registers~1262\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1390 Register_File:inst29\|registers~1390 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1390\" merged to single register \"Register_File:inst29\|registers~1390\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~108 Register_File:inst29\|registers~108 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~108\" merged to single register \"Register_File:inst29\|registers~108\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~364 Register_File:inst29\|registers~364 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~364\" merged to single register \"Register_File:inst29\|registers~364\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1388 Register_File:inst29\|registers~1388 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1388\" merged to single register \"Register_File:inst29\|registers~1388\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~106 Register_File:inst29\|registers~106 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~106\" merged to single register \"Register_File:inst29\|registers~106\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1130 Register_File:inst29\|registers~1130 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1130\" merged to single register \"Register_File:inst29\|registers~1130\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1386 Register_File:inst29\|registers~1386 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1386\" merged to single register \"Register_File:inst29\|registers~1386\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~104 Register_File:inst29\|registers~104 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~104\" merged to single register \"Register_File:inst29\|registers~104\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~360 Register_File:inst29\|registers~360 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~360\" merged to single register \"Register_File:inst29\|registers~360\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1128 Register_File:inst29\|registers~1128 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1128\" merged to single register \"Register_File:inst29\|registers~1128\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1384 Register_File:inst29\|registers~1384 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1384\" merged to single register \"Register_File:inst29\|registers~1384\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~102 Register_File:inst29\|registers~102 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~102\" merged to single register \"Register_File:inst29\|registers~102\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~358 Register_File:inst29\|registers~358 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~358\" merged to single register \"Register_File:inst29\|registers~358\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1126 Register_File:inst29\|registers~1126 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1126\" merged to single register \"Register_File:inst29\|registers~1126\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1382 Register_File:inst29\|registers~1382 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1382\" merged to single register \"Register_File:inst29\|registers~1382\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~100 Register_File:inst29\|registers~100 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~100\" merged to single register \"Register_File:inst29\|registers~100\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~356 Register_File:inst29\|registers~356 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~356\" merged to single register \"Register_File:inst29\|registers~356\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1124 Register_File:inst29\|registers~1124 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1124\" merged to single register \"Register_File:inst29\|registers~1124\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1380 Register_File:inst29\|registers~1380 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1380\" merged to single register \"Register_File:inst29\|registers~1380\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~98 Register_File:inst29\|registers~98 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~98\" merged to single register \"Register_File:inst29\|registers~98\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~354 Register_File:inst29\|registers~354 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~354\" merged to single register \"Register_File:inst29\|registers~354\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1378 Register_File:inst29\|registers~1378 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1378\" merged to single register \"Register_File:inst29\|registers~1378\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~96 Register_File:inst29\|registers~96 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~96\" merged to single register \"Register_File:inst29\|registers~96\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~224 Register_File:inst29\|registers~224 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~224\" merged to single register \"Register_File:inst29\|registers~224\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~352 Register_File:inst29\|registers~352 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~352\" merged to single register \"Register_File:inst29\|registers~352\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~480 Register_File:inst29\|registers~480 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~480\" merged to single register \"Register_File:inst29\|registers~480\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1120 Register_File:inst29\|registers~1120 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1120\" merged to single register \"Register_File:inst29\|registers~1120\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1248 Register_File:inst29\|registers~1248 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1248\" merged to single register \"Register_File:inst29\|registers~1248\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1376 Register_File:inst29\|registers~1376 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1376\" merged to single register \"Register_File:inst29\|registers~1376\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1504 Register_File:inst29\|registers~1504 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1504\" merged to single register \"Register_File:inst29\|registers~1504\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~94 Register_File:inst29\|registers~94 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~94\" merged to single register \"Register_File:inst29\|registers~94\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~222 Register_File:inst29\|registers~222 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~222\" merged to single register \"Register_File:inst29\|registers~222\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~350 Register_File:inst29\|registers~350 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~350\" merged to single register \"Register_File:inst29\|registers~350\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~478 Register_File:inst29\|registers~478 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~478\" merged to single register \"Register_File:inst29\|registers~478\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1246 Register_File:inst29\|registers~1246 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1246\" merged to single register \"Register_File:inst29\|registers~1246\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1374 Register_File:inst29\|registers~1374 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1374\" merged to single register \"Register_File:inst29\|registers~1374\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1502 Register_File:inst29\|registers~1502 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1502\" merged to single register \"Register_File:inst29\|registers~1502\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~92 Register_File:inst29\|registers~92 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~92\" merged to single register \"Register_File:inst29\|registers~92\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~156 Register_File:inst29\|registers~156 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~156\" merged to single register \"Register_File:inst29\|registers~156\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~220 Register_File:inst29\|registers~220 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~220\" merged to single register \"Register_File:inst29\|registers~220\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~284 Register_File:inst29\|registers~284 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~284\" merged to single register \"Register_File:inst29\|registers~284\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~348 Register_File:inst29\|registers~348 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~348\" merged to single register \"Register_File:inst29\|registers~348\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~412 Register_File:inst29\|registers~412 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~412\" merged to single register \"Register_File:inst29\|registers~412\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~476 Register_File:inst29\|registers~476 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~476\" merged to single register \"Register_File:inst29\|registers~476\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~540 Register_File:inst29\|registers~540 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~540\" merged to single register \"Register_File:inst29\|registers~540\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1116 Register_File:inst29\|registers~1116 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1116\" merged to single register \"Register_File:inst29\|registers~1116\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1180 Register_File:inst29\|registers~1180 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1180\" merged to single register \"Register_File:inst29\|registers~1180\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1244 Register_File:inst29\|registers~1244 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1244\" merged to single register \"Register_File:inst29\|registers~1244\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1308 Register_File:inst29\|registers~1308 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1308\" merged to single register \"Register_File:inst29\|registers~1308\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1372 Register_File:inst29\|registers~1372 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1372\" merged to single register \"Register_File:inst29\|registers~1372\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1436 Register_File:inst29\|registers~1436 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1436\" merged to single register \"Register_File:inst29\|registers~1436\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1500 Register_File:inst29\|registers~1500 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1500\" merged to single register \"Register_File:inst29\|registers~1500\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1564 Register_File:inst29\|registers~1564 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1564\" merged to single register \"Register_File:inst29\|registers~1564\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~90 Register_File:inst29\|registers~90 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~90\" merged to single register \"Register_File:inst29\|registers~90\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~154 Register_File:inst29\|registers~154 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~154\" merged to single register \"Register_File:inst29\|registers~154\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~218 Register_File:inst29\|registers~218 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~218\" merged to single register \"Register_File:inst29\|registers~218\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~282 Register_File:inst29\|registers~282 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~282\" merged to single register \"Register_File:inst29\|registers~282\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~346 Register_File:inst29\|registers~346 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~346\" merged to single register \"Register_File:inst29\|registers~346\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~410 Register_File:inst29\|registers~410 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~410\" merged to single register \"Register_File:inst29\|registers~410\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~474 Register_File:inst29\|registers~474 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~474\" merged to single register \"Register_File:inst29\|registers~474\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~538 Register_File:inst29\|registers~538 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~538\" merged to single register \"Register_File:inst29\|registers~538\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1178 Register_File:inst29\|registers~1178 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1178\" merged to single register \"Register_File:inst29\|registers~1178\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1242 Register_File:inst29\|registers~1242 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1242\" merged to single register \"Register_File:inst29\|registers~1242\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1306 Register_File:inst29\|registers~1306 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1306\" merged to single register \"Register_File:inst29\|registers~1306\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1370 Register_File:inst29\|registers~1370 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1370\" merged to single register \"Register_File:inst29\|registers~1370\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1434 Register_File:inst29\|registers~1434 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1434\" merged to single register \"Register_File:inst29\|registers~1434\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1498 Register_File:inst29\|registers~1498 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1498\" merged to single register \"Register_File:inst29\|registers~1498\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1562 Register_File:inst29\|registers~1562 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1562\" merged to single register \"Register_File:inst29\|registers~1562\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~86 Register_File:inst29\|registers~86 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~86\" merged to single register \"Register_File:inst29\|registers~86\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~150 Register_File:inst29\|registers~150 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~150\" merged to single register \"Register_File:inst29\|registers~150\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~214 Register_File:inst29\|registers~214 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~214\" merged to single register \"Register_File:inst29\|registers~214\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~278 Register_File:inst29\|registers~278 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~278\" merged to single register \"Register_File:inst29\|registers~278\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~342 Register_File:inst29\|registers~342 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~342\" merged to single register \"Register_File:inst29\|registers~342\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~406 Register_File:inst29\|registers~406 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~406\" merged to single register \"Register_File:inst29\|registers~406\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~470 Register_File:inst29\|registers~470 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~470\" merged to single register \"Register_File:inst29\|registers~470\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~534 Register_File:inst29\|registers~534 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~534\" merged to single register \"Register_File:inst29\|registers~534\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1110 Register_File:inst29\|registers~1110 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1110\" merged to single register \"Register_File:inst29\|registers~1110\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1174 Register_File:inst29\|registers~1174 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1174\" merged to single register \"Register_File:inst29\|registers~1174\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1238 Register_File:inst29\|registers~1238 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1238\" merged to single register \"Register_File:inst29\|registers~1238\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1302 Register_File:inst29\|registers~1302 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1302\" merged to single register \"Register_File:inst29\|registers~1302\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1366 Register_File:inst29\|registers~1366 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1366\" merged to single register \"Register_File:inst29\|registers~1366\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1430 Register_File:inst29\|registers~1430 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1430\" merged to single register \"Register_File:inst29\|registers~1430\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1494 Register_File:inst29\|registers~1494 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1494\" merged to single register \"Register_File:inst29\|registers~1494\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1558 Register_File:inst29\|registers~1558 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1558\" merged to single register \"Register_File:inst29\|registers~1558\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~84 Register_File:inst29\|registers~84 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~84\" merged to single register \"Register_File:inst29\|registers~84\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~148 Register_File:inst29\|registers~148 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~148\" merged to single register \"Register_File:inst29\|registers~148\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~212 Register_File:inst29\|registers~212 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~212\" merged to single register \"Register_File:inst29\|registers~212\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~276 Register_File:inst29\|registers~276 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~276\" merged to single register \"Register_File:inst29\|registers~276\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~340 Register_File:inst29\|registers~340 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~340\" merged to single register \"Register_File:inst29\|registers~340\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~404 Register_File:inst29\|registers~404 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~404\" merged to single register \"Register_File:inst29\|registers~404\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~468 Register_File:inst29\|registers~468 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~468\" merged to single register \"Register_File:inst29\|registers~468\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~532 Register_File:inst29\|registers~532 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~532\" merged to single register \"Register_File:inst29\|registers~532\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1172 Register_File:inst29\|registers~1172 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1172\" merged to single register \"Register_File:inst29\|registers~1172\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1236 Register_File:inst29\|registers~1236 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1236\" merged to single register \"Register_File:inst29\|registers~1236\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1300 Register_File:inst29\|registers~1300 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1300\" merged to single register \"Register_File:inst29\|registers~1300\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1364 Register_File:inst29\|registers~1364 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1364\" merged to single register \"Register_File:inst29\|registers~1364\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1428 Register_File:inst29\|registers~1428 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1428\" merged to single register \"Register_File:inst29\|registers~1428\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1492 Register_File:inst29\|registers~1492 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1492\" merged to single register \"Register_File:inst29\|registers~1492\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1556 Register_File:inst29\|registers~1556 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1556\" merged to single register \"Register_File:inst29\|registers~1556\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~82 Register_File:inst29\|registers~82 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~82\" merged to single register \"Register_File:inst29\|registers~82\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~210 Register_File:inst29\|registers~210 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~210\" merged to single register \"Register_File:inst29\|registers~210\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~338 Register_File:inst29\|registers~338 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~338\" merged to single register \"Register_File:inst29\|registers~338\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~466 Register_File:inst29\|registers~466 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~466\" merged to single register \"Register_File:inst29\|registers~466\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1234 Register_File:inst29\|registers~1234 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1234\" merged to single register \"Register_File:inst29\|registers~1234\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1362 Register_File:inst29\|registers~1362 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1362\" merged to single register \"Register_File:inst29\|registers~1362\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1490 Register_File:inst29\|registers~1490 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1490\" merged to single register \"Register_File:inst29\|registers~1490\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~80 Register_File:inst29\|registers~80 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~80\" merged to single register \"Register_File:inst29\|registers~80\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1104 Register_File:inst29\|registers~1104 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1104\" merged to single register \"Register_File:inst29\|registers~1104\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~78 Register_File:inst29\|registers~78 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~78\" merged to single register \"Register_File:inst29\|registers~78\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1102 Register_File:inst29\|registers~1102 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1102\" merged to single register \"Register_File:inst29\|registers~1102\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~76 Register_File:inst29\|registers~76 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~76\" merged to single register \"Register_File:inst29\|registers~76\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1100 Register_File:inst29\|registers~1100 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1100\" merged to single register \"Register_File:inst29\|registers~1100\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~74 Register_File:inst29\|registers~74 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~74\" merged to single register \"Register_File:inst29\|registers~74\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1098 Register_File:inst29\|registers~1098 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1098\" merged to single register \"Register_File:inst29\|registers~1098\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~72 Register_File:inst29\|registers~72 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~72\" merged to single register \"Register_File:inst29\|registers~72\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1096 Register_File:inst29\|registers~1096 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1096\" merged to single register \"Register_File:inst29\|registers~1096\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~70 Register_File:inst29\|registers~70 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~70\" merged to single register \"Register_File:inst29\|registers~70\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1094 Register_File:inst29\|registers~1094 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1094\" merged to single register \"Register_File:inst29\|registers~1094\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~68 Register_File:inst29\|registers~68 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~68\" merged to single register \"Register_File:inst29\|registers~68\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1092 Register_File:inst29\|registers~1092 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1092\" merged to single register \"Register_File:inst29\|registers~1092\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~66 Register_File:inst29\|registers~66 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~66\" merged to single register \"Register_File:inst29\|registers~66\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1090 Register_File:inst29\|registers~1090 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1090\" merged to single register \"Register_File:inst29\|registers~1090\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~64 Register_File:inst29\|registers~64 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~64\" merged to single register \"Register_File:inst29\|registers~64\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1528 Register_File:inst29\|registers~1528 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1528\" merged to single register \"Register_File:inst29\|registers~1528\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1212 Register_File:inst29\|registers~1212 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1212\" merged to single register \"Register_File:inst29\|registers~1212\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1468 Register_File:inst29\|registers~1468 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1468\" merged to single register \"Register_File:inst29\|registers~1468\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1260 Register_File:inst29\|registers~1260 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1260\" merged to single register \"Register_File:inst29\|registers~1260\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~484 Register_File:inst29\|registers~484 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~484\" merged to single register \"Register_File:inst29\|registers~484\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~482 Register_File:inst29\|registers~482 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~482\" merged to single register \"Register_File:inst29\|registers~482\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1250 Register_File:inst29\|registers~1250 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1250\" merged to single register \"Register_File:inst29\|registers~1250\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~416 Register_File:inst29\|registers~416 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~416\" merged to single register \"Register_File:inst29\|registers~416\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1184 Register_File:inst29\|registers~1184 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1184\" merged to single register \"Register_File:inst29\|registers~1184\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1440 Register_File:inst29\|registers~1440 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1440\" merged to single register \"Register_File:inst29\|registers~1440\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~158 Register_File:inst29\|registers~158 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~158\" merged to single register \"Register_File:inst29\|registers~158\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~414 Register_File:inst29\|registers~414 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~414\" merged to single register \"Register_File:inst29\|registers~414\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1310 Register_File:inst29\|registers~1310 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1310\" merged to single register \"Register_File:inst29\|registers~1310\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1566 Register_File:inst29\|registers~1566 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1566\" merged to single register \"Register_File:inst29\|registers~1566\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~208 Register_File:inst29\|registers~208 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~208\" merged to single register \"Register_File:inst29\|registers~208\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~322 Register_File:inst29\|registers~322 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~322\" merged to single register \"Register_File:inst29\|registers~322\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1148 Register_File:inst29\|registers~1148 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1148\" merged to single register \"Register_File:inst29\|registers~1148\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1340 Register_File:inst29\|registers~1340 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1340\" merged to single register \"Register_File:inst29\|registers~1340\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~186 Register_File:inst29\|registers~186 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~186\" merged to single register \"Register_File:inst29\|registers~186\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~308 Register_File:inst29\|registers~308 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~308\" merged to single register \"Register_File:inst29\|registers~308\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1332 Register_File:inst29\|registers~1332 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1332\" merged to single register \"Register_File:inst29\|registers~1332\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1138 Register_File:inst29\|registers~1138 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1138\" merged to single register \"Register_File:inst29\|registers~1138\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1584 Register_File:inst29\|registers~1584 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1584\" merged to single register \"Register_File:inst29\|registers~1584\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~558 Register_File:inst29\|registers~558 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~558\" merged to single register \"Register_File:inst29\|registers~558\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1196 Register_File:inst29\|registers~1196 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1196\" merged to single register \"Register_File:inst29\|registers~1196\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1580 Register_File:inst29\|registers~1580 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1580\" merged to single register \"Register_File:inst29\|registers~1580\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1194 Register_File:inst29\|registers~1194 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1194\" merged to single register \"Register_File:inst29\|registers~1194\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1190 Register_File:inst29\|registers~1190 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1190\" merged to single register \"Register_File:inst29\|registers~1190\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~548 Register_File:inst29\|registers~548 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~548\" merged to single register \"Register_File:inst29\|registers~548\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~544 Register_File:inst29\|registers~544 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~544\" merged to single register \"Register_File:inst29\|registers~544\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~542 Register_File:inst29\|registers~542 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~542\" merged to single register \"Register_File:inst29\|registers~542\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1118 Register_File:inst29\|registers~1118 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1118\" merged to single register \"Register_File:inst29\|registers~1118\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1554 Register_File:inst29\|registers~1554 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1554\" merged to single register \"Register_File:inst29\|registers~1554\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~400 Register_File:inst29\|registers~400 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~400\" merged to single register \"Register_File:inst29\|registers~400\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~270 Register_File:inst29\|registers~270 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~270\" merged to single register \"Register_File:inst29\|registers~270\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~140 Register_File:inst29\|registers~140 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~140\" merged to single register \"Register_File:inst29\|registers~140\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~136 Register_File:inst29\|registers~136 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~136\" merged to single register \"Register_File:inst29\|registers~136\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1154 Register_File:inst29\|registers~1154 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1154\" merged to single register \"Register_File:inst29\|registers~1154\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1410 Register_File:inst29\|registers~1410 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1410\" merged to single register \"Register_File:inst29\|registers~1410\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~384 Register_File:inst29\|registers~384 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~384\" merged to single register \"Register_File:inst29\|registers~384\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1210 Register_File:inst29\|registers~1210 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1210\" merged to single register \"Register_File:inst29\|registers~1210\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1206 Register_File:inst29\|registers~1206 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1206\" merged to single register \"Register_File:inst29\|registers~1206\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1448 Register_File:inst29\|registers~1448 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1448\" merged to single register \"Register_File:inst29\|registers~1448\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~290 Register_File:inst29\|registers~290 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~290\" merged to single register \"Register_File:inst29\|registers~290\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1442 Register_File:inst29\|registers~1442 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1442\" merged to single register \"Register_File:inst29\|registers~1442\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1570 Register_File:inst29\|registers~1570 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1570\" merged to single register \"Register_File:inst29\|registers~1570\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1568 Register_File:inst29\|registers~1568 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1568\" merged to single register \"Register_File:inst29\|registers~1568\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1114 Register_File:inst29\|registers~1114 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1114\" merged to single register \"Register_File:inst29\|registers~1114\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~142 Register_File:inst29\|registers~142 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~142\" merged to single register \"Register_File:inst29\|registers~142\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1158 Register_File:inst29\|registers~1158 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1158\" merged to single register \"Register_File:inst29\|registers~1158\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1414 Register_File:inst29\|registers~1414 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1414\" merged to single register \"Register_File:inst29\|registers~1414\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~128 Register_File:inst29\|registers~128 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~128\" merged to single register \"Register_File:inst29\|registers~128\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1594 Register_File:inst29\|registers~1594 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1594\" merged to single register \"Register_File:inst29\|registers~1594\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~438 Register_File:inst29\|registers~438 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~438\" merged to single register \"Register_File:inst29\|registers~438\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~180 Register_File:inst29\|registers~180 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~180\" merged to single register \"Register_File:inst29\|registers~180\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~564 Register_File:inst29\|registers~564 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~564\" merged to single register \"Register_File:inst29\|registers~564\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~430 Register_File:inst29\|registers~430 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~430\" merged to single register \"Register_File:inst29\|registers~430\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~556 Register_File:inst29\|registers~556 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~556\" merged to single register \"Register_File:inst29\|registers~556\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~424 Register_File:inst29\|registers~424 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~424\" merged to single register \"Register_File:inst29\|registers~424\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~166 Register_File:inst29\|registers~166 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~166\" merged to single register \"Register_File:inst29\|registers~166\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1446 Register_File:inst29\|registers~1446 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1446\" merged to single register \"Register_File:inst29\|registers~1446\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~288 Register_File:inst29\|registers~288 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~288\" merged to single register \"Register_File:inst29\|registers~288\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~134 Register_File:inst29\|registers~134 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~134\" merged to single register \"Register_File:inst29\|registers~134\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~182 Register_File:inst29\|registers~182 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~182\" merged to single register \"Register_File:inst29\|registers~182\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1460 Register_File:inst29\|registers~1460 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1460\" merged to single register \"Register_File:inst29\|registers~1460\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~300 Register_File:inst29\|registers~300 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~300\" merged to single register \"Register_File:inst29\|registers~300\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1192 Register_File:inst29\|registers~1192 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1192\" merged to single register \"Register_File:inst29\|registers~1192\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~162 Register_File:inst29\|registers~162 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~162\" merged to single register \"Register_File:inst29\|registers~162\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1314 Register_File:inst29\|registers~1314 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1314\" merged to single register \"Register_File:inst29\|registers~1314\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1506 Register_File:inst29\|registers~1506 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1506\" merged to single register \"Register_File:inst29\|registers~1506\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~160 Register_File:inst29\|registers~160 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~160\" merged to single register \"Register_File:inst29\|registers~160\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~286 Register_File:inst29\|registers~286 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~286\" merged to single register \"Register_File:inst29\|registers~286\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1438 Register_File:inst29\|registers~1438 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1438\" merged to single register \"Register_File:inst29\|registers~1438\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1164 Register_File:inst29\|registers~1164 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1164\" merged to single register \"Register_File:inst29\|registers~1164\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~392 Register_File:inst29\|registers~392 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~392\" merged to single register \"Register_File:inst29\|registers~392\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1156 Register_File:inst29\|registers~1156 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1156\" merged to single register \"Register_File:inst29\|registers~1156\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1412 Register_File:inst29\|registers~1412 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1412\" merged to single register \"Register_File:inst29\|registers~1412\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1152 Register_File:inst29\|registers~1152 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1152\" merged to single register \"Register_File:inst29\|registers~1152\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1408 Register_File:inst29\|registers~1408 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1408\" merged to single register \"Register_File:inst29\|registers~1408\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~174 Register_File:inst29\|registers~174 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~174\" merged to single register \"Register_File:inst29\|registers~174\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1326 Register_File:inst29\|registers~1326 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1326\" merged to single register \"Register_File:inst29\|registers~1326\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~170 Register_File:inst29\|registers~170 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~170\" merged to single register \"Register_File:inst29\|registers~170\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~168 Register_File:inst29\|registers~168 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~168\" merged to single register \"Register_File:inst29\|registers~168\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~546 Register_File:inst29\|registers~546 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~546\" merged to single register \"Register_File:inst29\|registers~546\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1122 Register_File:inst29\|registers~1122 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1122\" merged to single register \"Register_File:inst29\|registers~1122\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1186 Register_File:inst29\|registers~1186 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1186\" merged to single register \"Register_File:inst29\|registers~1186\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~146 Register_File:inst29\|registers~146 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~146\" merged to single register \"Register_File:inst29\|registers~146\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~528 Register_File:inst29\|registers~528 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~528\" merged to single register \"Register_File:inst29\|registers~528\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~138 Register_File:inst29\|registers~138 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~138\" merged to single register \"Register_File:inst29\|registers~138\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~428 Register_File:inst29\|registers~428 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~428\" merged to single register \"Register_File:inst29\|registers~428\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1312 Register_File:inst29\|registers~1312 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1312\" merged to single register \"Register_File:inst29\|registers~1312\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~144 Register_File:inst29\|registers~144 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~144\" merged to single register \"Register_File:inst29\|registers~144\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1168 Register_File:inst29\|registers~1168 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1168\" merged to single register \"Register_File:inst29\|registers~1168\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1424 Register_File:inst29\|registers~1424 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1424\" merged to single register \"Register_File:inst29\|registers~1424\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1166 Register_File:inst29\|registers~1166 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1166\" merged to single register \"Register_File:inst29\|registers~1166\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1420 Register_File:inst29\|registers~1420 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1420\" merged to single register \"Register_File:inst29\|registers~1420\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~250 Register_File:inst29\|registers~250 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~250\" merged to single register \"Register_File:inst29\|registers~250\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1318 Register_File:inst29\|registers~1318 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1318\" merged to single register \"Register_File:inst29\|registers~1318\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1444 Register_File:inst29\|registers~1444 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1444\" merged to single register \"Register_File:inst29\|registers~1444\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1572 Register_File:inst29\|registers~1572 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1572\" merged to single register \"Register_File:inst29\|registers~1572\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~402 Register_File:inst29\|registers~402 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~402\" merged to single register \"Register_File:inst29\|registers~402\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1298 Register_File:inst29\|registers~1298 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1298\" merged to single register \"Register_File:inst29\|registers~1298\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~398 Register_File:inst29\|registers~398 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~398\" merged to single register \"Register_File:inst29\|registers~398\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~390 Register_File:inst29\|registers~390 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~390\" merged to single register \"Register_File:inst29\|registers~390\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~132 Register_File:inst29\|registers~132 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~132\" merged to single register \"Register_File:inst29\|registers~132\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~130 Register_File:inst29\|registers~130 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~130\" merged to single register \"Register_File:inst29\|registers~130\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1280 Register_File:inst29\|registers~1280 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1280\" merged to single register \"Register_File:inst29\|registers~1280\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1588 Register_File:inst29\|registers~1588 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1588\" merged to single register \"Register_File:inst29\|registers~1588\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1582 Register_File:inst29\|registers~1582 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1582\" merged to single register \"Register_File:inst29\|registers~1582\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1574 Register_File:inst29\|registers~1574 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1574\" merged to single register \"Register_File:inst29\|registers~1574\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~530 Register_File:inst29\|registers~530 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~530\" merged to single register \"Register_File:inst29\|registers~530\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~394 Register_File:inst29\|registers~394 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~394\" merged to single register \"Register_File:inst29\|registers~394\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~256 Register_File:inst29\|registers~256 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~256\" merged to single register \"Register_File:inst29\|registers~256\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1536 Register_File:inst29\|registers~1536 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1536\" merged to single register \"Register_File:inst29\|registers~1536\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1198 Register_File:inst29\|registers~1198 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1198\" merged to single register \"Register_File:inst29\|registers~1198\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1452 Register_File:inst29\|registers~1452 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1452\" merged to single register \"Register_File:inst29\|registers~1452\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~164 Register_File:inst29\|registers~164 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~164\" merged to single register \"Register_File:inst29\|registers~164\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~292 Register_File:inst29\|registers~292 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~292\" merged to single register \"Register_File:inst29\|registers~292\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1316 Register_File:inst29\|registers~1316 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1316\" merged to single register \"Register_File:inst29\|registers~1316\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~272 Register_File:inst29\|registers~272 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~272\" merged to single register \"Register_File:inst29\|registers~272\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1454 Register_File:inst29\|registers~1454 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1454\" merged to single register \"Register_File:inst29\|registers~1454\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1450 Register_File:inst29\|registers~1450 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1450\" merged to single register \"Register_File:inst29\|registers~1450\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1188 Register_File:inst29\|registers~1188 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1188\" merged to single register \"Register_File:inst29\|registers~1188\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~226 Register_File:inst29\|registers~226 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~226\" merged to single register \"Register_File:inst29\|registers~226\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1162 Register_File:inst29\|registers~1162 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1162\" merged to single register \"Register_File:inst29\|registers~1162\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1160 Register_File:inst29\|registers~1160 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1160\" merged to single register \"Register_File:inst29\|registers~1160\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1416 Register_File:inst29\|registers~1416 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1416\" merged to single register \"Register_File:inst29\|registers~1416\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1282 Register_File:inst29\|registers~1282 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1282\" merged to single register \"Register_File:inst29\|registers~1282\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~504 Register_File:inst29\|registers~504 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~504\" merged to single register \"Register_File:inst29\|registers~504\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~440 Register_File:inst29\|registers~440 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~440\" merged to single register \"Register_File:inst29\|registers~440\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~376 Register_File:inst29\|registers~376 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~376\" merged to single register \"Register_File:inst29\|registers~376\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~568 Register_File:inst29\|registers~568 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~568\" merged to single register \"Register_File:inst29\|registers~568\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~184 Register_File:inst29\|registers~184 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~184\" merged to single register \"Register_File:inst29\|registers~184\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~248 Register_File:inst29\|registers~248 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~248\" merged to single register \"Register_File:inst29\|registers~248\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~312 Register_File:inst29\|registers~312 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~312\" merged to single register \"Register_File:inst29\|registers~312\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1464 Register_File:inst29\|registers~1464 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1464\" merged to single register \"Register_File:inst29\|registers~1464\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1208 Register_File:inst29\|registers~1208 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1208\" merged to single register \"Register_File:inst29\|registers~1208\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1272 Register_File:inst29\|registers~1272 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1272\" merged to single register \"Register_File:inst29\|registers~1272\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1400 Register_File:inst29\|registers~1400 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1400\" merged to single register \"Register_File:inst29\|registers~1400\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1592 Register_File:inst29\|registers~1592 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1592\" merged to single register \"Register_File:inst29\|registers~1592\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1336 Register_File:inst29\|registers~1336 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1336\" merged to single register \"Register_File:inst29\|registers~1336\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~408 Register_File:inst29\|registers~408 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~408\" merged to single register \"Register_File:inst29\|registers~408\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~472 Register_File:inst29\|registers~472 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~472\" merged to single register \"Register_File:inst29\|registers~472\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~536 Register_File:inst29\|registers~536 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~536\" merged to single register \"Register_File:inst29\|registers~536\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~152 Register_File:inst29\|registers~152 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~152\" merged to single register \"Register_File:inst29\|registers~152\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~88 Register_File:inst29\|registers~88 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~88\" merged to single register \"Register_File:inst29\|registers~88\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1560 Register_File:inst29\|registers~1560 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1560\" merged to single register \"Register_File:inst29\|registers~1560\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1596 Register_File:inst29\|registers~1596 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1596\" merged to single register \"Register_File:inst29\|registers~1596\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~446 Register_File:inst29\|registers~446 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~446\" merged to single register \"Register_File:inst29\|registers~446\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~574 Register_File:inst29\|registers~574 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~574\" merged to single register \"Register_File:inst29\|registers~574\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~254 Register_File:inst29\|registers~254 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~254\" merged to single register \"Register_File:inst29\|registers~254\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~190 Register_File:inst29\|registers~190 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~190\" merged to single register \"Register_File:inst29\|registers~190\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~318 Register_File:inst29\|registers~318 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~318\" merged to single register \"Register_File:inst29\|registers~318\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1214 Register_File:inst29\|registers~1214 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1214\" merged to single register \"Register_File:inst29\|registers~1214\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1182 Register_File:inst29\|registers~1182 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1182\" merged to single register \"Register_File:inst29\|registers~1182\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~442 Register_File:inst29\|registers~442 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~442\" merged to single register \"Register_File:inst29\|registers~442\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~506 Register_File:inst29\|registers~506 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~506\" merged to single register \"Register_File:inst29\|registers~506\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~570 Register_File:inst29\|registers~570 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~570\" merged to single register \"Register_File:inst29\|registers~570\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~314 Register_File:inst29\|registers~314 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~314\" merged to single register \"Register_File:inst29\|registers~314\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1530 Register_File:inst29\|registers~1530 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1530\" merged to single register \"Register_File:inst29\|registers~1530\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1274 Register_File:inst29\|registers~1274 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1274\" merged to single register \"Register_File:inst29\|registers~1274\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1466 Register_File:inst29\|registers~1466 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1466\" merged to single register \"Register_File:inst29\|registers~1466\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1146 Register_File:inst29\|registers~1146 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1146\" merged to single register \"Register_File:inst29\|registers~1146\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1338 Register_File:inst29\|registers~1338 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1338\" merged to single register \"Register_File:inst29\|registers~1338\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~464 Register_File:inst29\|registers~464 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~464\" merged to single register \"Register_File:inst29\|registers~464\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~336 Register_File:inst29\|registers~336 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~336\" merged to single register \"Register_File:inst29\|registers~336\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1488 Register_File:inst29\|registers~1488 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1488\" merged to single register \"Register_File:inst29\|registers~1488\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1232 Register_File:inst29\|registers~1232 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1232\" merged to single register \"Register_File:inst29\|registers~1232\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1360 Register_File:inst29\|registers~1360 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1360\" merged to single register \"Register_File:inst29\|registers~1360\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1552 Register_File:inst29\|registers~1552 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1552\" merged to single register \"Register_File:inst29\|registers~1552\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1296 Register_File:inst29\|registers~1296 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1296\" merged to single register \"Register_File:inst29\|registers~1296\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~436 Register_File:inst29\|registers~436 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~436\" merged to single register \"Register_File:inst29\|registers~436\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1204 Register_File:inst29\|registers~1204 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1204\" merged to single register \"Register_File:inst29\|registers~1204\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1108 Register_File:inst29\|registers__dual~1108 " "Info: Duplicate register \"Register_File:inst29\|registers~1108\" merged to single register \"Register_File:inst29\|registers__dual~1108\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~502 Register_File:inst29\|registers~502 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~502\" merged to single register \"Register_File:inst29\|registers~502\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~566 Register_File:inst29\|registers~566 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~566\" merged to single register \"Register_File:inst29\|registers~566\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~246 Register_File:inst29\|registers~246 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~246\" merged to single register \"Register_File:inst29\|registers~246\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~310 Register_File:inst29\|registers~310 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~310\" merged to single register \"Register_File:inst29\|registers~310\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1462 Register_File:inst29\|registers~1462 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1462\" merged to single register \"Register_File:inst29\|registers~1462\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1526 Register_File:inst29\|registers~1526 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1526\" merged to single register \"Register_File:inst29\|registers~1526\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1270 Register_File:inst29\|registers~1270 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1270\" merged to single register \"Register_File:inst29\|registers~1270\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1590 Register_File:inst29\|registers~1590 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1590\" merged to single register \"Register_File:inst29\|registers~1590\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1334 Register_File:inst29\|registers~1334 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1334\" merged to single register \"Register_File:inst29\|registers~1334\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~274 Register_File:inst29\|registers~274 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~274\" merged to single register \"Register_File:inst29\|registers~274\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1426 Register_File:inst29\|registers~1426 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1426\" merged to single register \"Register_File:inst29\|registers~1426\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1170 Register_File:inst29\|registers~1170 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1170\" merged to single register \"Register_File:inst29\|registers~1170\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1106 Register_File:inst29\|registers~1106 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1106\" merged to single register \"Register_File:inst29\|registers~1106\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~488 Register_File:inst29\|registers~488 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~488\" merged to single register \"Register_File:inst29\|registers~488\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~552 Register_File:inst29\|registers~552 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~552\" merged to single register \"Register_File:inst29\|registers~552\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~232 Register_File:inst29\|registers~232 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~232\" merged to single register \"Register_File:inst29\|registers~232\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~296 Register_File:inst29\|registers~296 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~296\" merged to single register \"Register_File:inst29\|registers~296\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1512 Register_File:inst29\|registers~1512 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1512\" merged to single register \"Register_File:inst29\|registers~1512\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1256 Register_File:inst29\|registers~1256 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1256\" merged to single register \"Register_File:inst29\|registers~1256\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1576 Register_File:inst29\|registers~1576 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1576\" merged to single register \"Register_File:inst29\|registers~1576\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1320 Register_File:inst29\|registers~1320 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1320\" merged to single register \"Register_File:inst29\|registers~1320\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~456 Register_File:inst29\|registers~456 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~456\" merged to single register \"Register_File:inst29\|registers~456\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~328 Register_File:inst29\|registers~328 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~328\" merged to single register \"Register_File:inst29\|registers~328\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~520 Register_File:inst29\|registers~520 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~520\" merged to single register \"Register_File:inst29\|registers~520\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~200 Register_File:inst29\|registers~200 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~200\" merged to single register \"Register_File:inst29\|registers~200\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~264 Register_File:inst29\|registers~264 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~264\" merged to single register \"Register_File:inst29\|registers~264\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1480 Register_File:inst29\|registers~1480 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1480\" merged to single register \"Register_File:inst29\|registers~1480\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1224 Register_File:inst29\|registers~1224 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1224\" merged to single register \"Register_File:inst29\|registers~1224\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1352 Register_File:inst29\|registers~1352 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1352\" merged to single register \"Register_File:inst29\|registers~1352\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1544 Register_File:inst29\|registers~1544 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1544\" merged to single register \"Register_File:inst29\|registers~1544\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1288 Register_File:inst29\|registers~1288 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1288\" merged to single register \"Register_File:inst29\|registers~1288\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~492 Register_File:inst29\|registers~492 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~492\" merged to single register \"Register_File:inst29\|registers~492\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~236 Register_File:inst29\|registers~236 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~236\" merged to single register \"Register_File:inst29\|registers~236\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~172 Register_File:inst29\|registers~172 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~172\" merged to single register \"Register_File:inst29\|registers~172\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1516 Register_File:inst29\|registers~1516 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1516\" merged to single register \"Register_File:inst29\|registers~1516\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1132 Register_File:inst29\|registers~1132 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1132\" merged to single register \"Register_File:inst29\|registers~1132\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1324 Register_File:inst29\|registers~1324 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1324\" merged to single register \"Register_File:inst29\|registers~1324\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~460 Register_File:inst29\|registers~460 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~460\" merged to single register \"Register_File:inst29\|registers~460\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~396 Register_File:inst29\|registers~396 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~396\" merged to single register \"Register_File:inst29\|registers~396\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~332 Register_File:inst29\|registers~332 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~332\" merged to single register \"Register_File:inst29\|registers~332\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~524 Register_File:inst29\|registers~524 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~524\" merged to single register \"Register_File:inst29\|registers~524\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~204 Register_File:inst29\|registers~204 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~204\" merged to single register \"Register_File:inst29\|registers~204\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~268 Register_File:inst29\|registers~268 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~268\" merged to single register \"Register_File:inst29\|registers~268\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1484 Register_File:inst29\|registers~1484 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1484\" merged to single register \"Register_File:inst29\|registers~1484\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1228 Register_File:inst29\|registers~1228 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1228\" merged to single register \"Register_File:inst29\|registers~1228\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1356 Register_File:inst29\|registers~1356 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1356\" merged to single register \"Register_File:inst29\|registers~1356\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1548 Register_File:inst29\|registers~1548 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1548\" merged to single register \"Register_File:inst29\|registers~1548\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1292 Register_File:inst29\|registers~1292 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1292\" merged to single register \"Register_File:inst29\|registers~1292\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~302 Register_File:inst29\|registers~302 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~302\" merged to single register \"Register_File:inst29\|registers~302\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1518 Register_File:inst29\|registers~1518 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1518\" merged to single register \"Register_File:inst29\|registers~1518\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1134 Register_File:inst29\|registers~1134 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1134\" merged to single register \"Register_File:inst29\|registers~1134\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~462 Register_File:inst29\|registers~462 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~462\" merged to single register \"Register_File:inst29\|registers~462\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~334 Register_File:inst29\|registers~334 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~334\" merged to single register \"Register_File:inst29\|registers~334\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~526 Register_File:inst29\|registers~526 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~526\" merged to single register \"Register_File:inst29\|registers~526\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~206 Register_File:inst29\|registers~206 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~206\" merged to single register \"Register_File:inst29\|registers~206\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1486 Register_File:inst29\|registers~1486 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1486\" merged to single register \"Register_File:inst29\|registers~1486\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1230 Register_File:inst29\|registers~1230 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1230\" merged to single register \"Register_File:inst29\|registers~1230\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1422 Register_File:inst29\|registers~1422 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1422\" merged to single register \"Register_File:inst29\|registers~1422\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1358 Register_File:inst29\|registers~1358 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1358\" merged to single register \"Register_File:inst29\|registers~1358\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1550 Register_File:inst29\|registers~1550 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1550\" merged to single register \"Register_File:inst29\|registers~1550\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1294 Register_File:inst29\|registers~1294 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1294\" merged to single register \"Register_File:inst29\|registers~1294\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~490 Register_File:inst29\|registers~490 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~490\" merged to single register \"Register_File:inst29\|registers~490\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~426 Register_File:inst29\|registers~426 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~426\" merged to single register \"Register_File:inst29\|registers~426\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~362 Register_File:inst29\|registers~362 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~362\" merged to single register \"Register_File:inst29\|registers~362\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~554 Register_File:inst29\|registers~554 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~554\" merged to single register \"Register_File:inst29\|registers~554\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~234 Register_File:inst29\|registers~234 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~234\" merged to single register \"Register_File:inst29\|registers~234\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~298 Register_File:inst29\|registers~298 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~298\" merged to single register \"Register_File:inst29\|registers~298\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1514 Register_File:inst29\|registers~1514 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1514\" merged to single register \"Register_File:inst29\|registers~1514\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1258 Register_File:inst29\|registers~1258 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1258\" merged to single register \"Register_File:inst29\|registers~1258\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1578 Register_File:inst29\|registers~1578 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1578\" merged to single register \"Register_File:inst29\|registers~1578\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1322 Register_File:inst29\|registers~1322 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1322\" merged to single register \"Register_File:inst29\|registers~1322\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~458 Register_File:inst29\|registers~458 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~458\" merged to single register \"Register_File:inst29\|registers~458\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~330 Register_File:inst29\|registers~330 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~330\" merged to single register \"Register_File:inst29\|registers~330\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~522 Register_File:inst29\|registers~522 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~522\" merged to single register \"Register_File:inst29\|registers~522\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~202 Register_File:inst29\|registers~202 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~202\" merged to single register \"Register_File:inst29\|registers~202\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~266 Register_File:inst29\|registers~266 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~266\" merged to single register \"Register_File:inst29\|registers~266\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1482 Register_File:inst29\|registers~1482 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1482\" merged to single register \"Register_File:inst29\|registers~1482\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1226 Register_File:inst29\|registers~1226 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1226\" merged to single register \"Register_File:inst29\|registers~1226\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1418 Register_File:inst29\|registers~1418 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1418\" merged to single register \"Register_File:inst29\|registers~1418\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1354 Register_File:inst29\|registers~1354 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1354\" merged to single register \"Register_File:inst29\|registers~1354\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1546 Register_File:inst29\|registers~1546 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1546\" merged to single register \"Register_File:inst29\|registers~1546\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1290 Register_File:inst29\|registers~1290 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1290\" merged to single register \"Register_File:inst29\|registers~1290\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1216 Register_File:inst29\|registers__dual~1216 " "Info: Duplicate register \"Register_File:inst29\|registers~1216\" merged to single register \"Register_File:inst29\|registers__dual~1216\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~448 Register_File:inst29\|registers__dual~448 " "Info: Duplicate register \"Register_File:inst29\|registers~448\" merged to single register \"Register_File:inst29\|registers__dual~448\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~192 Register_File:inst29\|registers__dual~192 " "Info: Duplicate register \"Register_File:inst29\|registers~192\" merged to single register \"Register_File:inst29\|registers__dual~192\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1472 Register_File:inst29\|registers__dual~1472 " "Info: Duplicate register \"Register_File:inst29\|registers~1472\" merged to single register \"Register_File:inst29\|registers__dual~1472\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1088 Register_File:inst29\|registers__dual~1088 " "Info: Duplicate register \"Register_File:inst29\|registers~1088\" merged to single register \"Register_File:inst29\|registers__dual~1088\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~320 Register_File:inst29\|registers__dual~320 " "Info: Duplicate register \"Register_File:inst29\|registers~320\" merged to single register \"Register_File:inst29\|registers__dual~320\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1344 Register_File:inst29\|registers__dual~1344 " "Info: Duplicate register \"Register_File:inst29\|registers~1344\" merged to single register \"Register_File:inst29\|registers__dual~1344\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~512 Register_File:inst29\|registers__dual~512 " "Info: Duplicate register \"Register_File:inst29\|registers~512\" merged to single register \"Register_File:inst29\|registers__dual~512\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~420 Register_File:inst29\|registers~420 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~420\" merged to single register \"Register_File:inst29\|registers~420\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~228 Register_File:inst29\|registers~228 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~228\" merged to single register \"Register_File:inst29\|registers~228\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1508 Register_File:inst29\|registers~1508 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1508\" merged to single register \"Register_File:inst29\|registers~1508\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1252 Register_File:inst29\|registers~1252 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1252\" merged to single register \"Register_File:inst29\|registers~1252\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~452 Register_File:inst29\|registers~452 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~452\" merged to single register \"Register_File:inst29\|registers~452\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~388 Register_File:inst29\|registers~388 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~388\" merged to single register \"Register_File:inst29\|registers~388\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~324 Register_File:inst29\|registers~324 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~324\" merged to single register \"Register_File:inst29\|registers~324\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~516 Register_File:inst29\|registers~516 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~516\" merged to single register \"Register_File:inst29\|registers~516\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~196 Register_File:inst29\|registers~196 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~196\" merged to single register \"Register_File:inst29\|registers~196\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~260 Register_File:inst29\|registers~260 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~260\" merged to single register \"Register_File:inst29\|registers~260\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1476 Register_File:inst29\|registers~1476 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1476\" merged to single register \"Register_File:inst29\|registers~1476\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1220 Register_File:inst29\|registers~1220 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1220\" merged to single register \"Register_File:inst29\|registers~1220\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1348 Register_File:inst29\|registers~1348 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1348\" merged to single register \"Register_File:inst29\|registers~1348\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1540 Register_File:inst29\|registers~1540 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1540\" merged to single register \"Register_File:inst29\|registers~1540\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~1284 Register_File:inst29\|registers~1284 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~1284\" merged to single register \"Register_File:inst29\|registers~1284\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~486 Register_File:inst29\|registers__dual~486 " "Info: Duplicate register \"Register_File:inst29\|registers~486\" merged to single register \"Register_File:inst29\|registers__dual~486\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1254 Register_File:inst29\|registers__dual~1254 " "Info: Duplicate register \"Register_File:inst29\|registers~1254\" merged to single register \"Register_File:inst29\|registers__dual~1254\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~230 Register_File:inst29\|registers__dual~230 " "Info: Duplicate register \"Register_File:inst29\|registers~230\" merged to single register \"Register_File:inst29\|registers__dual~230\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1510 Register_File:inst29\|registers__dual~1510 " "Info: Duplicate register \"Register_File:inst29\|registers~1510\" merged to single register \"Register_File:inst29\|registers__dual~1510\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~422 Register_File:inst29\|registers__dual~422 " "Info: Duplicate register \"Register_File:inst29\|registers~422\" merged to single register \"Register_File:inst29\|registers__dual~422\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~550 Register_File:inst29\|registers__dual~550 " "Info: Duplicate register \"Register_File:inst29\|registers~550\" merged to single register \"Register_File:inst29\|registers__dual~550\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~294 Register_File:inst29\|registers__dual~294 " "Info: Duplicate register \"Register_File:inst29\|registers~294\" merged to single register \"Register_File:inst29\|registers__dual~294\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1222 Register_File:inst29\|registers__dual~1222 " "Info: Duplicate register \"Register_File:inst29\|registers~1222\" merged to single register \"Register_File:inst29\|registers__dual~1222\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1286 Register_File:inst29\|registers__dual~1286 " "Info: Duplicate register \"Register_File:inst29\|registers~1286\" merged to single register \"Register_File:inst29\|registers__dual~1286\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~454 Register_File:inst29\|registers__dual~454 " "Info: Duplicate register \"Register_File:inst29\|registers~454\" merged to single register \"Register_File:inst29\|registers__dual~454\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~326 Register_File:inst29\|registers__dual~326 " "Info: Duplicate register \"Register_File:inst29\|registers~326\" merged to single register \"Register_File:inst29\|registers__dual~326\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~518 Register_File:inst29\|registers__dual~518 " "Info: Duplicate register \"Register_File:inst29\|registers~518\" merged to single register \"Register_File:inst29\|registers__dual~518\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~198 Register_File:inst29\|registers__dual~198 " "Info: Duplicate register \"Register_File:inst29\|registers~198\" merged to single register \"Register_File:inst29\|registers__dual~198\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~262 Register_File:inst29\|registers__dual~262 " "Info: Duplicate register \"Register_File:inst29\|registers~262\" merged to single register \"Register_File:inst29\|registers__dual~262\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1478 Register_File:inst29\|registers__dual~1478 " "Info: Duplicate register \"Register_File:inst29\|registers~1478\" merged to single register \"Register_File:inst29\|registers__dual~1478\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1350 Register_File:inst29\|registers__dual~1350 " "Info: Duplicate register \"Register_File:inst29\|registers~1350\" merged to single register \"Register_File:inst29\|registers__dual~1350\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1542 Register_File:inst29\|registers__dual~1542 " "Info: Duplicate register \"Register_File:inst29\|registers~1542\" merged to single register \"Register_File:inst29\|registers__dual~1542\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~450 Register_File:inst29\|registers__dual~450 " "Info: Duplicate register \"Register_File:inst29\|registers~450\" merged to single register \"Register_File:inst29\|registers__dual~450\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~386 Register_File:inst29\|registers__dual~386 " "Info: Duplicate register \"Register_File:inst29\|registers~386\" merged to single register \"Register_File:inst29\|registers__dual~386\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~514 Register_File:inst29\|registers__dual~514 " "Info: Duplicate register \"Register_File:inst29\|registers~514\" merged to single register \"Register_File:inst29\|registers__dual~514\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1218 Register_File:inst29\|registers__dual~1218 " "Info: Duplicate register \"Register_File:inst29\|registers~1218\" merged to single register \"Register_File:inst29\|registers__dual~1218\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~194 Register_File:inst29\|registers__dual~194 " "Info: Duplicate register \"Register_File:inst29\|registers~194\" merged to single register \"Register_File:inst29\|registers__dual~194\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~258 Register_File:inst29\|registers__dual~258 " "Info: Duplicate register \"Register_File:inst29\|registers~258\" merged to single register \"Register_File:inst29\|registers__dual~258\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1474 Register_File:inst29\|registers__dual~1474 " "Info: Duplicate register \"Register_File:inst29\|registers~1474\" merged to single register \"Register_File:inst29\|registers__dual~1474\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1346 Register_File:inst29\|registers__dual~1346 " "Info: Duplicate register \"Register_File:inst29\|registers~1346\" merged to single register \"Register_File:inst29\|registers__dual~1346\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers~1538 Register_File:inst29\|registers__dual~1538 " "Info: Duplicate register \"Register_File:inst29\|registers~1538\" merged to single register \"Register_File:inst29\|registers__dual~1538\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Register_File:inst29\|registers__dual~418 Register_File:inst29\|registers~418 " "Info: Duplicate register \"Register_File:inst29\|registers__dual~418\" merged to single register \"Register_File:inst29\|registers~418\"" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_CE_N GND " "Warning (13410): Pin \"SRAM_CE_N\" stuck at GND" {  } { { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 680 672 848 696 "SRAM_CE_N" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_UB_N GND " "Warning (13410): Pin \"SRAM_UB_N\" stuck at GND" {  } { { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 728 672 848 744 "SRAM_UB_N" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_LB_N GND " "Warning (13410): Pin \"SRAM_LB_N\" stuck at GND" {  } { { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 744 672 848 760 "SRAM_LB_N" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAM_Addr\[17\] GND " "Warning (13410): Pin \"SRAM_Addr\[17\]\" stuck at GND" {  } { { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { { 664 672 857 680 "SRAM_Addr\[17..0\]" "" } { 656 560 672 672 "SRAM_Addr\[17..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "515 100 " "Info: 515 registers lost all their fanouts during netlist optimizations. The first 100 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Data_Memory:inst26\|curr_state~59 " "Info: Register \"Data_Memory:inst26\|curr_state~59\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Data_Memory:inst26\|curr_state~60 " "Info: Register \"Data_Memory:inst26\|curr_state~60\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Data_Memory:inst26\|curr_state~61 " "Info: Register \"Data_Memory:inst26\|curr_state~61\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~576 " "Info: Register \"Register_File:inst29\|registers__dual~576\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~578 " "Info: Register \"Register_File:inst29\|registers__dual~578\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~580 " "Info: Register \"Register_File:inst29\|registers__dual~580\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~582 " "Info: Register \"Register_File:inst29\|registers__dual~582\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~584 " "Info: Register \"Register_File:inst29\|registers__dual~584\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~586 " "Info: Register \"Register_File:inst29\|registers__dual~586\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~588 " "Info: Register \"Register_File:inst29\|registers__dual~588\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~590 " "Info: Register \"Register_File:inst29\|registers__dual~590\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~592 " "Info: Register \"Register_File:inst29\|registers__dual~592\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~594 " "Info: Register \"Register_File:inst29\|registers__dual~594\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~596 " "Info: Register \"Register_File:inst29\|registers__dual~596\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~598 " "Info: Register \"Register_File:inst29\|registers__dual~598\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~600 " "Info: Register \"Register_File:inst29\|registers__dual~600\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~602 " "Info: Register \"Register_File:inst29\|registers__dual~602\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~604 " "Info: Register \"Register_File:inst29\|registers__dual~604\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~606 " "Info: Register \"Register_File:inst29\|registers__dual~606\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~608 " "Info: Register \"Register_File:inst29\|registers__dual~608\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~610 " "Info: Register \"Register_File:inst29\|registers__dual~610\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~612 " "Info: Register \"Register_File:inst29\|registers__dual~612\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~614 " "Info: Register \"Register_File:inst29\|registers__dual~614\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~616 " "Info: Register \"Register_File:inst29\|registers__dual~616\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~618 " "Info: Register \"Register_File:inst29\|registers__dual~618\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~620 " "Info: Register \"Register_File:inst29\|registers__dual~620\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~622 " "Info: Register \"Register_File:inst29\|registers__dual~622\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~624 " "Info: Register \"Register_File:inst29\|registers__dual~624\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~626 " "Info: Register \"Register_File:inst29\|registers__dual~626\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~628 " "Info: Register \"Register_File:inst29\|registers__dual~628\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~630 " "Info: Register \"Register_File:inst29\|registers__dual~630\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~632 " "Info: Register \"Register_File:inst29\|registers__dual~632\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~634 " "Info: Register \"Register_File:inst29\|registers__dual~634\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~636 " "Info: Register \"Register_File:inst29\|registers__dual~636\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~638 " "Info: Register \"Register_File:inst29\|registers__dual~638\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~640 " "Info: Register \"Register_File:inst29\|registers__dual~640\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~642 " "Info: Register \"Register_File:inst29\|registers__dual~642\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~644 " "Info: Register \"Register_File:inst29\|registers__dual~644\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~646 " "Info: Register \"Register_File:inst29\|registers__dual~646\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~648 " "Info: Register \"Register_File:inst29\|registers__dual~648\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~650 " "Info: Register \"Register_File:inst29\|registers__dual~650\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~652 " "Info: Register \"Register_File:inst29\|registers__dual~652\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~654 " "Info: Register \"Register_File:inst29\|registers__dual~654\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~656 " "Info: Register \"Register_File:inst29\|registers__dual~656\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~658 " "Info: Register \"Register_File:inst29\|registers__dual~658\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~660 " "Info: Register \"Register_File:inst29\|registers__dual~660\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~662 " "Info: Register \"Register_File:inst29\|registers__dual~662\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~664 " "Info: Register \"Register_File:inst29\|registers__dual~664\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~666 " "Info: Register \"Register_File:inst29\|registers__dual~666\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~668 " "Info: Register \"Register_File:inst29\|registers__dual~668\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~670 " "Info: Register \"Register_File:inst29\|registers__dual~670\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~672 " "Info: Register \"Register_File:inst29\|registers__dual~672\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~674 " "Info: Register \"Register_File:inst29\|registers__dual~674\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~676 " "Info: Register \"Register_File:inst29\|registers__dual~676\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~678 " "Info: Register \"Register_File:inst29\|registers__dual~678\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~680 " "Info: Register \"Register_File:inst29\|registers__dual~680\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~682 " "Info: Register \"Register_File:inst29\|registers__dual~682\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~684 " "Info: Register \"Register_File:inst29\|registers__dual~684\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~686 " "Info: Register \"Register_File:inst29\|registers__dual~686\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~688 " "Info: Register \"Register_File:inst29\|registers__dual~688\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~690 " "Info: Register \"Register_File:inst29\|registers__dual~690\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~692 " "Info: Register \"Register_File:inst29\|registers__dual~692\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~694 " "Info: Register \"Register_File:inst29\|registers__dual~694\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~696 " "Info: Register \"Register_File:inst29\|registers__dual~696\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~698 " "Info: Register \"Register_File:inst29\|registers__dual~698\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~700 " "Info: Register \"Register_File:inst29\|registers__dual~700\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~702 " "Info: Register \"Register_File:inst29\|registers__dual~702\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~704 " "Info: Register \"Register_File:inst29\|registers__dual~704\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~706 " "Info: Register \"Register_File:inst29\|registers__dual~706\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~708 " "Info: Register \"Register_File:inst29\|registers__dual~708\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~710 " "Info: Register \"Register_File:inst29\|registers__dual~710\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~712 " "Info: Register \"Register_File:inst29\|registers__dual~712\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~714 " "Info: Register \"Register_File:inst29\|registers__dual~714\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~716 " "Info: Register \"Register_File:inst29\|registers__dual~716\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~718 " "Info: Register \"Register_File:inst29\|registers__dual~718\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~720 " "Info: Register \"Register_File:inst29\|registers__dual~720\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~722 " "Info: Register \"Register_File:inst29\|registers__dual~722\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~724 " "Info: Register \"Register_File:inst29\|registers__dual~724\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~726 " "Info: Register \"Register_File:inst29\|registers__dual~726\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~728 " "Info: Register \"Register_File:inst29\|registers__dual~728\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~730 " "Info: Register \"Register_File:inst29\|registers__dual~730\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~732 " "Info: Register \"Register_File:inst29\|registers__dual~732\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~734 " "Info: Register \"Register_File:inst29\|registers__dual~734\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~736 " "Info: Register \"Register_File:inst29\|registers__dual~736\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~738 " "Info: Register \"Register_File:inst29\|registers__dual~738\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~740 " "Info: Register \"Register_File:inst29\|registers__dual~740\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~742 " "Info: Register \"Register_File:inst29\|registers__dual~742\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~744 " "Info: Register \"Register_File:inst29\|registers__dual~744\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~746 " "Info: Register \"Register_File:inst29\|registers__dual~746\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~748 " "Info: Register \"Register_File:inst29\|registers__dual~748\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~750 " "Info: Register \"Register_File:inst29\|registers__dual~750\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~752 " "Info: Register \"Register_File:inst29\|registers__dual~752\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~754 " "Info: Register \"Register_File:inst29\|registers__dual~754\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~756 " "Info: Register \"Register_File:inst29\|registers__dual~756\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~758 " "Info: Register \"Register_File:inst29\|registers__dual~758\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~760 " "Info: Register \"Register_File:inst29\|registers__dual~760\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~762 " "Info: Register \"Register_File:inst29\|registers__dual~762\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~764 " "Info: Register \"Register_File:inst29\|registers__dual~764\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~766 " "Info: Register \"Register_File:inst29\|registers__dual~766\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Register_File:inst29\|registers__dual~768 " "Info: Register \"Register_File:inst29\|registers__dual~768\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_LIST_TRUNCATED" "100 " "Info: List truncated at 100 items" {  } {  } 0 0 "List truncated at %1!d! items" 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.map.smsg " "Info: Generated suppressed messages file F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2924 " "Info: Implemented 2924 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "69 " "Info: Implemented 69 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "2824 " "Info: Implemented 2824 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "166 " "Info: Allocated 166 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 02 19:54:16 2007 " "Info: Processing ended: Sun Dec 02 19:54:16 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Info: Elapsed time: 00:00:31" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
