{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 02 19:52:16 2007 " "Info: Processing started: Sun Dec 02 19:52:16 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off single_cycle_datapath -c single_cycle_datapath " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off single_cycle_datapath -c single_cycle_datapath" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hex2sevenseg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file hex2sevenseg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex2sevenseg " "Info: Found entity 1: hex2sevenseg" {  } { { "hex2sevenseg.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/hex2sevenseg.v" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "single_cycle_datapath.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file single_cycle_datapath.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 single_cycle_datapath " "Info: Found entity 1: single_cycle_datapath" {  } { { "single_cycle_datapath.bdf" "" { Schematic "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PC_Register.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file PC_Register.v" { { "Info" "ISGN_ENTITY_NAME" "1 PC_Register " "Info: Found entity 1: PC_Register" {  } { { "PC_Register.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/PC_Register.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "instruction_memory.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file instruction_memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 Instruction_Memory " "Info: Found entity 1: Instruction_Memory" {  } { { "instruction_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/instruction_memory.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Register_File.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Register_File.v" { { "Info" "ISGN_ENTITY_NAME" "1 Register_File " "Info: Found entity 1: Register_File" {  } { { "Register_File.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/Register_File.v" 12 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ALU.v" { { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Info: Found entity 1: ALU" {  } { { "ALU.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/ALU.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "r_format control_unit.v(45) " "Warning (10236): Verilog HDL Implicit Net warning at control_unit.v(45): created implicit net for \"r_format\"" {  } { { "control_unit.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/control_unit.v" 45 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "i_format control_unit.v(46) " "Warning (10236): Verilog HDL Implicit Net warning at control_unit.v(46): created implicit net for \"i_format\"" {  } { { "control_unit.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/control_unit.v" 46 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control_unit.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file control_unit.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_unit " "Info: Found entity 1: control_unit" {  } { { "control_unit.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/control_unit.v" 14 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "data_memory.v(65) " "Warning (10273): Verilog HDL warning at data_memory.v(65): extended using \"x\" or \"z\"" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 65 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "data_memory.v(76) " "Warning (10268): Verilog HDL information at data_memory.v(76): Always Construct contains both blocking and non-blocking assignments" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 76 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_memory.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 Data_Memory " "Info: Found entity 1: Data_Memory" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file add4.v" { { "Info" "ISGN_ENTITY_NAME" "1 add4 " "Info: Found entity 1: add4" {  } { { "add4.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/add4.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file alu_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu_control " "Info: Found entity 1: alu_control" {  } { { "alu_control.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/alu_control.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "calc_bta.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file calc_bta.v" { { "Info" "ISGN_ENTITY_NAME" "1 calc_BranchTargetAddress " "Info: Found entity 1: calc_BranchTargetAddress" {  } { { "calc_bta.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/calc_bta.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "calc_jump_address.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file calc_jump_address.v" { { "Info" "ISGN_ENTITY_NAME" "1 calc_JumpAddress " "Info: Found entity 1: calc_JumpAddress" {  } { { "calc_jump_address.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/calc_jump_address.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sign_extend_1632.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sign_extend_1632.v" { { "Info" "ISGN_ENTITY_NAME" "1 sign_extend_1632 " "Info: Found entity 1: sign_extend_1632" {  } { { "sign_extend_1632.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/sign_extend_1632.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "two_by_5_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file two_by_5_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 Two_by_5_mux " "Info: Found entity 1: Two_by_5_mux" {  } { { "two_by_5_mux.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/two_by_5_mux.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "two_by_16_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file two_by_16_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 Two_by_16_mux " "Info: Found entity 1: Two_by_16_mux" {  } { { "two_by_16_mux.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/two_by_16_mux.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "two_by_32_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file two_by_32_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 Two_by_32_mux " "Info: Found entity 1: Two_by_32_mux" {  } { { "two_by_32_mux.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/two_by_32_mux.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "eight_by_16_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file eight_by_16_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 Eight_by_16_mux " "Info: Found entity 1: Eight_by_16_mux" {  } { { "eight_by_16_mux.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/eight_by_16_mux.v" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pc_mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pc_mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 pc_mux " "Info: Found entity 1: pc_mux" {  } { { "pc_mux.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/pc_mux.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ledg_buffers.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ledg_buffers.v" { { "Info" "ISGN_ENTITY_NAME" "1 ledg_buffers " "Info: Found entity 1: ledg_buffers" {  } { { "ledg_buffers.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/ledg_buffers.v" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ledr_buffers.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ledr_buffers.v" { { "Info" "ISGN_ENTITY_NAME" "1 ledr_buffers " "Info: Found entity 1: ledr_buffers" {  } { { "ledr_buffers.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/ledr_buffers.v" 15 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_ILLEGAL_CONTINUOUS_ASSIGNMENT" "sram_upper_byte data_memory.v(64) " "Error (10219): Verilog HDL Continuous Assignment error at data_memory.v(64): object \"sram_upper_byte\" on left-hand side of assignment must have a net type" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 64 0 0 } }  } 0 10219 "Verilog HDL Continuous Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a net type" 0 0 "" 0}
{ "Error" "EVRFX_VERI_ILLEGAL_CONTINUOUS_ASSIGNMENT" "sram_lower_byte data_memory.v(64) " "Error (10219): Verilog HDL Continuous Assignment error at data_memory.v(64): object \"sram_lower_byte\" on left-hand side of assignment must have a net type" {  } { { "data_memory.v" "" { Text "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/data_memory.v" 64 0 0 } }  } 0 10219 "Verilog HDL Continuous Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a net type" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.map.smsg " "Info: Generated suppressed messages file F:/vickery On My Mac/Documents/Courses/FPGA_Projects/cs343/2007_02/Single_Cycle_Datapath/single_cycle_datapath.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "150 " "Info: Allocated 150 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sun Dec 02 19:52:20 2007 " "Error: Processing ended: Sun Dec 02 19:52:20 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:04 " "Error: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 2 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 2 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
